1. Field of the Invention
The present invention relates to a liquid crystal display device and a liquid crystal projector apparatus and, particularly a liquid crystal display device having a pixel board on which a light shielding film, a first insulating film, a semiconductor layer, a second insulating film serving as a gate insulating film and gate lines are formed, a source region, a drain region and a channel region or both of a channel region and LDD (Light doped drain) region being formed in the semiconductor layer, and a liquid crystal projector apparatus using the liquid crystal display device.
2. Description of the Related Art
Japanese Patent Application No. Hei-11-109979 discloses a pixel structure as a light shielding mechanism of liquid crystal light valve. FIG. 1 is a plan view showing a pixel TFT portion disclosed in Japanese Patent Application No. Hei-11-109979, and FIG. 2 is a cross-sectional view taken along a line E-E′ of FIG. 1.
As shown in FIGS. 1 and 2, ground film (ground insulating film) 14, back side light shielding film 3, first interlayer film 10, a semiconductor layer, gate insulating film 11, gate line 4, second insulating film 12, data line 5, third insulating film 13, black matrix 9 are formed on glass substrate 15. A source region, a drain region, channel region 1 and LDD region 2 are formed in the semiconductor layer.
As shown in FIG. 1, gate lines 4 and data lines 5 are arranged in a matrix form so as to be perpendicular to each other, and each pixel TFT is disposed at the intersecting portion between each gate line 4 and each data line 5. As shown in the cross-sectional view of FIG. 2, dummy contact hole 20 which does not reach a back side light shielding film 3 is formed in the neighborhood of the side surface of the LDD region 2 of each TFT. A gate line material is filled in the dummy contact hole 20. The dummy contact hole 20 serves to reduce light irradiated to the LDD region 2 of TFT. The potential of the back side light shielding film 3 is set to the ground (GND) potential so that the back side light shielding film 3 is prevented from acting as a back gate of TFT. The source region of TFT is connected to data line 5 through contact hole 7. The drain region of TFT is connected to a transparent pixel electrode ITO through contact hole 8.
Japanese Patent Application No. Hei-11-360973 discloses another pixel structure for the pixel light shielding mechanism of liquid crystal light valve. FIG. 3 is a plan view showing a pixel disclosed in Japanese Patent Application No. Hei-11-360973, and FIG. 4 is a cross-sectional view taken along a line F-F′ of FIG. 3. In FIGS. 3 and 4, when the function of the constituent member is the same as that of FIGS. 1 and 2, the same sign is put.
In the pixel structure of Japanese Patent Application No. Hei-11-360973, a contact hole 18 which reaches back side light shielding film 3 is formed at each of both the sides of TFT, and it is covered by aluminum wire 5 serving as a data line. The light 16′ irradiates to the contact holes 18. The TFT is shielded from the light by the contact holes 18. Side wall 19 is formed on the wall of the contact holes 18. Poly-Si (polysilicon) 21 is formed on ground film 14.
Japanese Laid-open Patent Publication Nos. Hei-1-128534, Hei-1-177020, Hei-8-62579 and Hei-8-234239 disclose techniques relating to the present invention. Particularly, Japanese Laid-open Patent Publication No. Hei-8-234239 discloses that a light shielding pattern and a gate wiring pattern are electrically connected to each other through a contact portion.
The structure of the Japanese Patent Application No. Hei-11-109979 cannot perfectly shield TFT from light irradiated to TFT, and thus it is difficult to prevent degradation in image quality due to optical leak current of TFT. Further, when the wire resistance of the gate lines is high, there occurs degradation in image quality due to delay of gate signals.
Further, the structure of Japanese Patent Application No. Hei-11-360973 can shield TFT from light irradiated to TFT, however, when the resistance of the gate lines is high, degradation in image quality due to the delay of the gate signals occurs.
The cause of the degradation in image quality will be described in detail.
In the pixel structure of the Japanese Patent Application No. Hei-11-109979, dummy contact holes which do not reach the back side light shielding film are formed at both the sides of the LDD region of TFT, and thus a gap occurs between the back side light shielding film and each dummy contact hole. Therefore, TFT cannot be perfectly shielded from light irradiated thereto.
In general, when a panel is designed in a compact size and the width of the wires is small, the wire resistance is increased. The embodiments disclosed in the Japanese Laid-open Patent Application Nos. Hei-11-109979 and Hei-11-360973 use WSi for the gate lines and aluminum wires for the data lines. WSi is higher in resistance than aluminum. Therefore, when the wire resistance is increased due to compact design of panels, the delay of the gate signals is also increased, and degradation in image quality due to this delay occurs.